We are looking for a talented VLSI Engineer that wishes to be a part of the VLSI team focusing on a virtualized 5G/NR base station.
Requirements:
- B.Sc. in Electrical Engineering
- Min 2 years experience as front-end engineer for ASIC designs
- Experience with Verilog design coding
- Experience with block level verification and full chip verification
- Ability and experience with legacy code understanding, debugging and a problem-solving attitude
- Experience with FPGA tools (prefer Xilinx Vivado)
- Scripting ability (perl / TCL/ csh) is an advantage
- Experience with Synthesis and STA analysis is a plus
Please send your resume to hr@asocscloud.com